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You have searched for paketit that names contain yosys in kaikki jakelut, kaikki osastot, and architecture(s) riscv64. Found 5 matching packages.
Tarkat hakutulokset
Paketti yosys
- sid (unstable) (electronics):
Framework for Verilog RTL synthesis
0.33-5+b3: riscv64 - experimental (electronics):
Framework for Verilog RTL synthesis
0.33-6~exp2+b1: riscv64
Muut hakutulokset
Paketti yosys-abc
- sid (unstable) (electronics):
Sequential Logic Synthesis and Verification Algorithms
0.33-5+b3: riscv64 - experimental (electronics):
Sequential Logic Synthesis and Verification Algorithms
0.33-6~exp2+b1: riscv64
Paketti yosys-dbgsym
- sid (unstable) (debug):
debug symbols for yosys
0.23-6 [debports]: riscv64
Paketti yosys-dev
- sid (unstable) (electronics):
Framework for Verilog RTL synthesis (development files)
0.33-5+b3: riscv64 - experimental (electronics):
Framework for Verilog RTL synthesis (development files)
0.33-6~exp2+b1: riscv64
Paketti yosys-doc
- buster (oldoldstable) (doc):
Documentation for Yosys
0.8-1: all - bullseye (oldstable) (doc):
Documentation for Yosys
0.9-1: all - bookworm (stable) (doc):
Documentation for Yosys
0.23-6: all - sid (unstable) (doc):
Framework for Verilog RTL synthesis (documentation)
0.33-5: all - experimental (doc):
Framework for Verilog RTL synthesis (documentation)
0.33-6~exp2: all