Limit to suite: [jessie] [jessie-updates] [stretch] [stretch-updates] [stretch-backports] [stretch-backports-sloppy] [buster] [buster-updates] [buster-backports] [bullseye] [sid] [experimental]
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You have searched for packages that names contain yosys in all suites, all sections, and all architectures. Found 4 matching packages.
Exact hits
Package yosys
- stretch (oldstable) (electronics):
Framework for Verilog RTL synthesis
0.7-2+deb9u1: amd64 arm64 armel armhf i386 mips mips64el mipsel ppc64el s390x - stretch-backports (electronics):
Framework for Verilog RTL synthesis
0.8-1~bpo9+1: amd64 arm64 armel armhf i386 mips mips64el mipsel ppc64el s390x - buster (stable) (electronics):
Framework for Verilog RTL synthesis
0.8-1: amd64 arm64 armel armhf i386 mips mips64el mipsel ppc64el s390x - buster-backports (electronics):
Framework for Verilog RTL synthesis
0.9-1~bpo10+1: amd64 arm64 armel armhf i386 mips mips64el mipsel ppc64el s390x - bullseye (testing) (electronics):
Framework for Verilog RTL synthesis
0.9-1+b1: amd64 arm64 armel armhf i386 mips64el mipsel ppc64el s390x - sid (unstable) (electronics):
Framework for Verilog RTL synthesis
0.9-1+b1: alpha amd64 arm64 armel armhf i386 m68k mips64el mipsel ppc64 ppc64el riscv64 s390x sh4 x32
0.8-1 [debports]: powerpcspe
0.7-7 [debports]: hppa
0.6-7+b1 [debports]: sparc64 - experimental (electronics):
Framework for Verilog RTL synthesis
0.8+20190328git32bd0f2-1~exp1 [debports]: powerpcspe
Other hits
Package yosys-dbgsym
- sid (unstable) (debug):
debug symbols for yosys
0.9-1+b1 [debports]: alpha m68k ppc64 riscv64 sh4 x32
0.8-1 [debports]: powerpcspe
0.7-7 [debports]: hppa
0.6-7+b1 [debports]: sparc64 - experimental (debug):
debug symbols for yosys
0.8+20190328git32bd0f2-1~exp1 [debports]: powerpcspe
Package yosys-dev
- stretch (oldstable) (electronics):
Framework for Verilog RTL synthesis (development files)
0.7-2+deb9u1: amd64 arm64 armel armhf i386 mips mips64el mipsel ppc64el s390x - stretch-backports (electronics):
Framework for Verilog RTL synthesis (development files)
0.8-1~bpo9+1: amd64 arm64 armel armhf i386 mips mips64el mipsel ppc64el s390x - buster (stable) (electronics):
Framework for Verilog RTL synthesis (development files)
0.8-1: amd64 arm64 armel armhf i386 mips mips64el mipsel ppc64el s390x - buster-backports (electronics):
Framework for Verilog RTL synthesis (development files)
0.9-1~bpo10+1: amd64 arm64 armel armhf i386 mips mips64el mipsel ppc64el s390x - bullseye (testing) (electronics):
Framework for Verilog RTL synthesis (development files)
0.9-1+b1: amd64 arm64 armel armhf i386 mips64el mipsel ppc64el s390x - sid (unstable) (electronics):
Framework for Verilog RTL synthesis (development files)
0.9-1+b1: alpha amd64 arm64 armel armhf i386 m68k mips64el mipsel ppc64 ppc64el riscv64 s390x sh4 x32
0.8-1 [debports]: powerpcspe
0.7-7 [debports]: hppa
0.6-7+b1 [debports]: sparc64 - experimental (electronics):
Framework for Verilog RTL synthesis (development files)
0.8+20190328git32bd0f2-1~exp1 [debports]: powerpcspe
Package yosys-doc
- stretch (oldstable) (doc):
Documentation for Yosys
0.7-2+deb9u1: all - stretch-backports (doc):
Documentation for Yosys
0.8-1~bpo9+1: all - buster (stable) (doc):
Documentation for Yosys
0.8-1: all - buster-backports (doc):
Documentation for Yosys
0.9-1~bpo10+1: all - bullseye (testing) (doc):
Documentation for Yosys
0.9-1: all - sid (unstable) (doc):
Documentation for Yosys
0.9-1: all