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You have searched for packages that names contain yosys in all suites, all sections, and all architectures. Found 4 matching packages.
Exact hits
Package yosys
- stretch (oldoldstable) (electronics):
Framework for Verilog RTL synthesis
0.7-2+deb9u1: amd64 arm64 armel armhf i386 mips mips64el mipsel ppc64el s390x - stretch-backports (electronics):
Framework for Verilog RTL synthesis
0.8-1~bpo9+1: amd64 arm64 armel armhf i386 mips mips64el mipsel ppc64el s390x - buster (oldstable) (electronics):
Framework for Verilog RTL synthesis
0.8-1: amd64 arm64 armel armhf i386 mips mips64el mipsel ppc64el s390x - buster-backports (electronics):
Framework for Verilog RTL synthesis
0.9-1~bpo10+1: amd64 arm64 armel armhf i386 mips mips64el mipsel ppc64el s390x - bullseye (stable) (electronics):
Framework for Verilog RTL synthesis
0.9-1+b1: amd64 arm64 armel armhf i386 mips64el mipsel ppc64el s390x - sid (unstable) (electronics):
Framework for Verilog RTL synthesis
0.19-1: alpha amd64 arm64 armel armhf i386 ia64 m68k mipsel ppc64el riscv64 sh4 x32
0.12-1 [debports]: hppa mips64el
0.9-2+b1 [debports]: ppc64
0.6-7+b1 [debports]: sparc64 - experimental (electronics):
Framework for Verilog RTL synthesis
0.8+20190328git32bd0f2-1~exp1 [debports]: powerpcspe
Other hits
Package yosys-dbgsym
- sid (unstable) (debug):
debug symbols for yosys
0.19-1 [debports]: alpha ia64 m68k riscv64 sh4 x32
0.12-1 [debports]: hppa
0.9-2+b1 [debports]: ppc64
0.6-7+b1 [debports]: sparc64 - experimental (debug):
debug symbols for yosys
0.8+20190328git32bd0f2-1~exp1 [debports]: powerpcspe
Package yosys-dev
- stretch (oldoldstable) (electronics):
Framework for Verilog RTL synthesis (development files)
0.7-2+deb9u1: amd64 arm64 armel armhf i386 mips mips64el mipsel ppc64el s390x - stretch-backports (electronics):
Framework for Verilog RTL synthesis (development files)
0.8-1~bpo9+1: amd64 arm64 armel armhf i386 mips mips64el mipsel ppc64el s390x - buster (oldstable) (electronics):
Framework for Verilog RTL synthesis (development files)
0.8-1: amd64 arm64 armel armhf i386 mips mips64el mipsel ppc64el s390x - buster-backports (electronics):
Framework for Verilog RTL synthesis (development files)
0.9-1~bpo10+1: amd64 arm64 armel armhf i386 mips mips64el mipsel ppc64el s390x - bullseye (stable) (electronics):
Framework for Verilog RTL synthesis (development files)
0.9-1+b1: amd64 arm64 armel armhf i386 mips64el mipsel ppc64el s390x - sid (unstable) (electronics):
Framework for Verilog RTL synthesis (development files)
0.19-1: alpha amd64 arm64 armel armhf i386 ia64 m68k mipsel ppc64el riscv64 sh4 x32
0.12-1: hppa mips64el
0.9-2+b1 [debports]: ppc64
0.6-7+b1 [debports]: sparc64 - experimental (electronics):
Framework for Verilog RTL synthesis (development files)
0.8+20190328git32bd0f2-1~exp1 [debports]: powerpcspe
Package yosys-doc
- stretch (oldoldstable) (doc):
Documentation for Yosys
0.7-2+deb9u1: all - stretch-backports (doc):
Documentation for Yosys
0.8-1~bpo9+1: all - buster (oldstable) (doc):
Documentation for Yosys
0.8-1: all - buster-backports (doc):
Documentation for Yosys
0.9-1~bpo10+1: all - bullseye (stable) (doc):
Documentation for Yosys
0.9-1: all - sid (unstable) (doc):
Documentation for Yosys
0.19-1: all