Zawęź do gałęzi: [buster] [buster-updates] [buster-backports] [bullseye] [bullseye-updates] [bullseye-backports] [bookworm] [bookworm-updates] [bookworm-backports] [trixie] [sid] [experimental]
Zawęź do architektury [alpha] [amd64] [arm] [arm64] [armel] [armhf] [avr32] [hppa] [hurd-i386] [i386] [ia64] [kfreebsd-amd64] [kfreebsd-i386] [m68k] [mips] [mips64el] [mipsel] [powerpc] [powerpcspe] [ppc64] [ppc64el] [riscv64] [s390] [s390x] [sh4] [sparc] [sparc64] [x32]
Szukaj we wszystkich architekturach
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Szukano pakietów których nazwy zawierają yosys w wszystkich gałęziach, wszystkich sekcjach i architekturze: mips64el. Liczba pasujących pakietów: 5.
Dokładne dopasowania
Pakiet yosys
- bullseye (oldstable) (electronics):
Framework for Verilog RTL synthesis
0.9-1+b1: mips64el - bookworm (stable) (electronics):
Framework for Verilog RTL synthesis
0.23-6: mips64el - sid (unstable) (electronics):
Framework for Verilog RTL synthesis
0.33-5+b2: mips64el - experimental (electronics):
Framework for Verilog RTL synthesis
0.33-6~exp2: mips64el
Inne wyniki
Pakiet yosys-abc
- sid (unstable) (electronics):
Sequential Logic Synthesis and Verification Algorithms
0.33-5+b2: mips64el - experimental (electronics):
Sequential Logic Synthesis and Verification Algorithms
0.33-6~exp2: mips64el
Pakiet yosys-dev
- bullseye (oldstable) (electronics):
Framework for Verilog RTL synthesis (development files)
0.9-1+b1: mips64el - bookworm (stable) (electronics):
Framework for Verilog RTL synthesis (development files)
0.23-6: mips64el - sid (unstable) (electronics):
Framework for Verilog RTL synthesis (development files)
0.33-5+b2: mips64el - experimental (electronics):
Framework for Verilog RTL synthesis (development files)
0.33-6~exp2: mips64el
Pakiet yosys-doc
- buster (oldoldstable) (doc):
Documentation for Yosys
0.8-1: all - bullseye (oldstable) (doc):
Documentation for Yosys
0.9-1: all - bookworm (stable) (doc):
Documentation for Yosys
0.23-6: all - sid (unstable) (doc):
Framework for Verilog RTL synthesis (documentation)
0.33-5: all - experimental (doc):
Framework for Verilog RTL synthesis (documentation)
0.33-6~exp2: all
Pakiet yosys-plugin-ghdl
- sid (unstable) (electronics):
VHDL to RTL synthesis plugin using GHDL
0.0~git20211127.09a32cd-3: mips64el