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[ 原始碼: covered  ]

套件: covered (0.7.8-2)

covered 的相關超連結

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Verilog code coverage analysis tool

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

標籤: 領域: 電子學, 實做語言: C, 使用者介面: 命令行, X 視窗系統, 角色: 程式, Interface Toolkit: Tk, Purpose: Data Visualization, X 視窗系統: 應用程式

其他與 covered 有關的套件

  • 依賴
  • 推薦
  • 建議
  • enhances

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下載可用於所有硬體架構的
硬體架構 套件大小 安裝後大小 檔案
mipsel 761.5 kB2,508.0 kB [文件列表]