Package: yosys-abc (0.33-5 and others)

[ Source: yosys  ]

Sequential Logic Synthesis and Verification Algorithms

ABC is a system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.

This is a fork of berkeley-abc maintained by the YosysHQ team for use in the yosys RTL synthesis framework.

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• dep: libc6 (>= 2.34) [not alpha, sh4]

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  dep: libc6 (>= 2.37) [sh4]

• dep: libc6.1 (>= 2.34) [alpha]

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• dep: libgcc-s1 (>= 3.3.1) [not armel, armhf, m68k]

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  dep: libgcc-s1 (>= 3.5) [armel, armhf]

• dep: libgcc-s2 (>= 4.2.1) [m68k]

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• dep: libreadline8 (>= 6.0) [sh4, x32]

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• dep: libstdc++6 (>= 13.1)

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Download yosys-abc

Download for all available architectures

Architecture	Version	Package Size	Installed Size	Files
alpha (unofficial port)	0.33-5+b2	5,056.0 kB	17,179.0 kB	[list of files]
amd64	0.33-5+b2	5,315.4 kB	14,688.0 kB	[list of files]
arm64	0.33-5+b2	4,750.9 kB	14,504.0 kB	[list of files]
armel	0.33-5+b2	4,564.0 kB	13,830.0 kB	[list of files]
armhf	0.33-5+b2	4,726.5 kB	10,542.0 kB	[list of files]
i386	0.33-5+b2	5,544.8 kB	16,397.0 kB	[list of files]
m68k (unofficial port)	0.33-5+b2	5,145.3 kB	15,917.0 kB	[list of files]
mips64el	0.33-5+b2	4,868.0 kB	18,271.0 kB	[list of files]
ppc64el	0.33-5+b2	5,526.4 kB	18,473.0 kB	[list of files]
riscv64	0.33-5+b3	5,446.0 kB	13,108.0 kB	[list of files]
sh4 (unofficial port)	0.33-5	5,845.9 kB	13,852.0 kB	[list of files]
x32 (unofficial port)	0.33-5	5,311.6 kB	14,421.0 kB	[list of files]