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[ Source: yosys  ]

Package: yosys (0.33-5 and others)

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Framework for Verilog RTL synthesis

This is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base.

Other Packages Related to yosys

  • depends
  • recommends
  • suggests
  • enhances

Download yosys

Download for all available architectures
Architecture Version Package Size Installed Size Files
alpha (unofficial port) 0.33-5+b2 2,846.1 kB14,892.0 kB [list of files]
amd64 0.33-5+b2 2,951.5 kB12,434.0 kB [list of files]
arm64 0.33-5+b2 2,602.7 kB12,366.0 kB [list of files]
armel 0.33-5+b2 2,660.2 kB12,081.0 kB [list of files]
armhf 0.33-5+b2 2,745.0 kB10,189.0 kB [list of files]
hppa (unofficial port) 0.12-1 3,017.8 kB16,641.0 kB [list of files]
i386 0.33-5+b2 2,976.8 kB12,665.0 kB [list of files]
ia64 (unofficial port) 0.23-6 3,401.3 kB22,772.0 kB [list of files]
m68k (unofficial port) 0.33-5+b2 2,925.9 kB12,593.0 kB [list of files]
mips64el 0.33-5+b2 2,493.5 kB14,391.0 kB [list of files]
ppc64 (unofficial port) 0.9-2+b1 2,026.7 kB9,448.0 kB [list of files]
ppc64el 0.33-5+b2 2,713.0 kB13,262.0 kB [list of files]
riscv64 0.33-5+b3 2,921.5 kB11,706.0 kB [list of files]
sh4 (unofficial port) 0.33-5+b2 3,671.5 kB13,131.0 kB [list of files]
sparc64 (unofficial port) 0.6-7+b1 1,267.7 kB5,329.0 kB [list of files]
x32 (unofficial port) 0.33-5+b2 2,952.8 kB11,937.0 kB [list of files]