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[ Source: iverilog  ]

Package: verilog (0.9.7-1 and others)

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Icarus verilog compiler (transitional package)

Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

This is a dummy transitional package that will ensure a proper upgrade path. This package may be safely removed after upgrading.

Tags: Field: Electronics, Role: Metapackage

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Download verilog

Download for all available architectures
Architecture Version Package Size Installed Size Files
all 0.9.7-1 6.0 kB31.0 kB [list of files]
m68k (unofficial port) 0.8.6-1 782.9 kB2,252.0 kB [list of files]