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[ Source: gplcver  ]

Package: gplcver (2.12a-3 and others)

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Verilog simulator

Cver is a full 1995 IEEE P1364 standard Verilog simulator. It also implements some of the 2001 P1364 standard features. All three PLI interfaces (tf_, acc_, and vpi_) are implemented as defined in the IEEE 2001 P1364 LRM.

Tags: Software Development: Need an extra tag, Interpreter, Field: Electronics, Implemented in: implemented-in::c, role::program, Purpose: Simulating

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Download gplcver

Download for all available architectures
Architecture Version Package Size Installed Size Files
alpha (unofficial port) 2.12a-3 786.1 kB2,269.0 kB [list of files]
amd64 2.12a-3 823.1 kB1,966.0 kB [list of files]
arm64 2.12a-3 779.1 kB2,077.0 kB [list of files]
armel 2.12a-3 752.0 kB1,896.0 kB [list of files]
armhf 2.12a-3 758.5 kB1,480.0 kB [list of files]
hppa (unofficial port) 2.12a-3 753.6 kB1,911.0 kB [list of files]
i386 2.12a-3 867.0 kB2,170.0 kB [list of files]
ia64 (unofficial port) 2.12a-2 999.5 kB3,859.0 kB [list of files]
loong64 (unofficial port) 2.12a-3 801.4 kB2,093.0 kB [list of files]
m68k (unofficial port) 2.12a-3 637.9 kB1,677.0 kB [list of files]
mips64el 2.12a-3 751.1 kB2,343.0 kB [list of files]
ppc64 (unofficial port) 2.12a-3 843.8 kB2,591.0 kB [list of files]
ppc64el 2.12a-3 858.3 kB2,461.0 kB [list of files]
riscv64 2.12a-3 854.7 kB1,821.0 kB [list of files]
s390x 2.12a-3 848.5 kB2,205.0 kB [list of files]
sh4 (unofficial port) 2.12a-3 797.3 kB1,558.0 kB [list of files]
sparc64 (unofficial port) 2.12a-3 749.8 kB2,341.0 kB [list of files]
x32 (unofficial port) 2.12a-3 805.7 kB1,863.0 kB [list of files]