Package: yosys-abc (0.33-5 and others)

[ Source: yosys  ]

Sequential Logic Synthesis and Verification Algorithms

ABC is a system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.

This is a fork of berkeley-abc maintained by the YosysHQ team for use in the yosys RTL synthesis framework.

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Download yosys-abc

Download for all available architectures

Architecture	Version	Package Size	Installed Size	Files
amd64	0.33-5+b2	5,315.4 kB	14,688.0 kB	[list of files]
arm64	0.33-5+b2	4,750.9 kB	14,504.0 kB	[list of files]
armel	0.33-5	4,538.8 kB	13,601.0 kB	[list of files]
armhf	0.33-5	4,707.5 kB	10,365.0 kB	[list of files]
i386	0.33-5+b2	5,544.8 kB	16,397.0 kB	[list of files]
mips64el	0.33-5+b2	4,868.0 kB	18,271.0 kB	[list of files]
ppc64el	0.33-5+b2	5,526.4 kB	18,473.0 kB	[list of files]