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[ Source: gplcver  ]

Package: gplcver (2.12a-1.1 and others)

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Verilog simulator

Cver is a full 1995 IEEE P1364 standard Verilog simulator. It also implements some of the 2001 P1364 standard features. All three PLI interfaces (tf_, acc_, and vpi_) are implemented as defined in the IEEE 2001 P1364 LRM.


Tags: Software Development: Need an extra tag, Interpreter, Field: Electronics, Implemented in: implemented-in::c, role::program, Purpose: Simulating

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Download gplcver

Download for all available architectures
Architecture Version Package Size Installed Size Files
amd64 2.12a-1.1+b2 792.7 kB1,884.0 kB [list of files]
arm64 2.12a-1.1+b2 702.4 kB1,827.0 kB [list of files]
armel 2.12a-1.1+b2 712.8 kB1,807.0 kB [list of files]
armhf 2.12a-1.1+b2 723.7 kB1,387.0 kB [list of files]
i386 2.12a-1.1+b2 836.6 kB2,096.0 kB [list of files]
mips64el 2.12a-1.1+b2 728.8 kB2,320.0 kB [list of files]
mipsel 2.12a-1.1+b2 732.1 kB2,061.0 kB [list of files]
ppc64el 2.12a-1.1+b2 724.1 kB2,139.0 kB [list of files]
s390x 2.12a-1.1+b2 780.9 kB2,285.0 kB [list of files]