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[ Source: opensta  ]

Package: opensta (0~20191111gitc018cb2+dfsg-1.1 and others)

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Gate-level Static Timing Analyzer

After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs.

It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.

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Download opensta

Download for all available architectures
Architecture Version Package Size Installed Size Files
alpha (unofficial port) 0~20191111gitc018cb2+dfsg-1.1 783.1 kB4,416.0 kB [list of files]
amd64 0~20191111gitc018cb2+dfsg-1.1 882.4 kB4,104.0 kB [list of files]
arm64 0~20191111gitc018cb2+dfsg-1.1 785.1 kB4,155.0 kB [list of files]
armel 0~20191111gitc018cb2+dfsg-1.1 687.9 kB3,477.0 kB [list of files]
armhf 0~20191111gitc018cb2+dfsg-1.1 705.8 kB2,741.0 kB [list of files]
hppa (unofficial port) 0~20191111gitc018cb2+dfsg-1.1 791.8 kB4,102.0 kB [list of files]
i386 0~20191111gitc018cb2+dfsg-1.1 942.3 kB4,229.0 kB [list of files]
ia64 (unofficial port) 0~20191111gitc018cb2+dfsg-1 887.9 kB6,478.0 kB [list of files]
loong64 (unofficial port) 0~20191111gitc018cb2+dfsg-1.1 837.4 kB4,203.0 kB [list of files]
m68k (unofficial port) 0~20191111gitc018cb2+dfsg-1.1 809.8 kB3,901.0 kB [list of files]
mips64el 0~20191111gitc018cb2+dfsg-1.1 857.3 kB5,493.0 kB [list of files]
ppc64 (unofficial port) 0~20191111gitc018cb2+dfsg-1.1 886.8 kB5,499.0 kB [list of files]
ppc64el 0~20191111gitc018cb2+dfsg-1.1 918.7 kB5,115.0 kB [list of files]
riscv64 0~20191111gitc018cb2+dfsg-1.1 866.9 kB3,431.0 kB [list of files]
s390x 0~20191111gitc018cb2+dfsg-1.1 814.6 kB4,163.0 kB [list of files]
sh4 (unofficial port) 0~20191111gitc018cb2+dfsg-1.1 950.3 kB3,950.0 kB [list of files]
sparc64 (unofficial port) 0~20191111gitc018cb2+dfsg-1.1 662.9 kB4,161.0 kB [list of files]
x32 (unofficial port) 0~20191111gitc018cb2+dfsg-1.1 891.9 kB3,914.0 kB [list of files]