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[ Source: arachne-pnr  ]

Package: arachne-pnr (0.1+20190728gitc40fb22-3)

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Place and route tool for iCE40 family FPGAs

Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It accepts as input a technology-mapped netlist in BLIF format, as output by the Yosys synthesis suite for example. It currently targets the Lattice Semiconductor iCE40 family of FPGAs. Its output is a textual bitstream representation for assembly by the IceStorm icepack command. The output of icepack is a binary bitstream which can be uploaded to a hardware device.

Together, Yosys, arachne-pnr and IceStorm provide an fully open-source Verilog-to-bistream tool chain for iCE40 1K and 8K FPGA development.

The authors of arachne-pnr have now prepared its successor 'nextpnr'.

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Download arachne-pnr

Download for all available architectures
Architecture Package Size Installed Size Files
alpha (unofficial port) 202.5 kB792.0 kB [list of files]
amd64 213.6 kB655.0 kB [list of files]
arm64 182.7 kB599.0 kB [list of files]
armel 175.9 kB598.0 kB [list of files]
armhf 182.9 kB406.0 kB [list of files]
hppa (unofficial port) 202.1 kB612.0 kB [list of files]
i386 231.8 kB766.0 kB [list of files]
ia64 (unofficial port) 264.0 kB1,399.0 kB [list of files]
m68k (unofficial port) 202.0 kB654.0 kB [list of files]
mips64el 186.1 kB814.0 kB [list of files]
mipsel 188.1 kB809.0 kB [list of files]
ppc64 (unofficial port) 209.0 kB791.0 kB [list of files]
ppc64el 211.1 kB791.0 kB [list of files]
riscv64 (unofficial port) 196.4 kB480.0 kB [list of files]
s390x 185.9 kB671.0 kB [list of files]
sh4 (unofficial port) 262.1 kB662.0 kB [list of files]
sparc64 (unofficial port) 171.9 kB1,050.0 kB [list of files]
x32 (unofficial port) 217.7 kB630.0 kB [list of files]