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You have searched for packages that names contain yosys in all suites, all sections, and architecture(s) x32. Found 6 matching packages.
Exact hits
Package yosys
- sid (unstable) (electronics):
Framework for Verilog RTL synthesis
0.33-5 [debports]: x32 - experimental (electronics):
Framework for Verilog RTL synthesis
0.33-6~exp2 [debports]: x32
Other hits
Package yosys-abc
- sid (unstable) (electronics):
Sequential Logic Synthesis and Verification Algorithms
0.33-5 [debports]: x32 - experimental (electronics):
Sequential Logic Synthesis and Verification Algorithms
0.33-6~exp2 [debports]: x32
Package yosys-abc-dbgsym
- sid (unstable) (debug):
debug symbols for yosys-abc
0.33-5 [debports]: x32 - experimental (debug):
debug symbols for yosys-abc
0.33-6~exp2 [debports]: x32
Package yosys-dbgsym
- sid (unstable) (debug):
debug symbols for yosys
0.33-5 [debports]: x32 - experimental (debug):
debug symbols for yosys
0.33-6~exp2 [debports]: x32
Package yosys-dev
- sid (unstable) (electronics):
Framework for Verilog RTL synthesis (development files)
0.33-5 [debports]: x32 - experimental (electronics):
Framework for Verilog RTL synthesis (development files)
0.33-6~exp2 [debports]: x32
Package yosys-doc
- buster (oldoldstable) (doc):
Documentation for Yosys
0.8-1: all - bullseye (oldstable) (doc):
Documentation for Yosys
0.9-1: all - bookworm (stable) (doc):
Documentation for Yosys
0.23-6: all - trixie (testing) (doc):
Framework for Verilog RTL synthesis (documentation)
0.33-5: all - sid (unstable) (doc):
Framework for Verilog RTL synthesis (documentation)
0.33-5: all - experimental (doc):
Framework for Verilog RTL synthesis (documentation)
0.33-6~exp2: all