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Pakket: opensta (0~20191111gitc018cb2+dfsg-1)

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Gate-level Static Timing Analyzer

After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs.

It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.

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Pakket downloaden voor alle beschikbare platforms
Platform Pakketgrootte Geïnstalleerde grootte Bestanden
alpha (unofficial port) 781,7 kB4.360,0 kB [overzicht]
amd64 790,1 kB3.732,0 kB [overzicht]
arm64 716,8 kB3.663,0 kB [overzicht]
armel 628,9 kB3.101,0 kB [overzicht]
armhf 646,3 kB2.481,0 kB [overzicht]
hppa (unofficial port) 743,2 kB3.788,0 kB [overzicht]
i386 864,7 kB3.869,0 kB [overzicht]
ia64 (unofficial port) 887,9 kB6.478,0 kB [overzicht]
m68k (unofficial port) 754,1 kB3.589,0 kB [overzicht]
mips64el 830,0 kB5.310,0 kB [overzicht]
mipsel 835,4 kB4.885,0 kB [overzicht]
ppc64 (unofficial port) 823,7 kB5.179,0 kB [overzicht]
ppc64el 836,8 kB4.731,0 kB [overzicht]
riscv64 (unofficial port) 747,7 kB3.177,0 kB [overzicht]
s390x 698,8 kB3.875,0 kB [overzicht]
sh4 (unofficial port) 871,3 kB3.686,0 kB [overzicht]
sparc64 (unofficial port) 617,4 kB3.561,0 kB [overzicht]
x32 (unofficial port) 798,4 kB3.542,0 kB [overzicht]