Softwarepakketten in "experimental", Subsectie electronics
- gnucap (1:20230520-dev-1+b1 [amd64, arm64, armel, armhf, hppa, i386, ia64, m68k, mips64el, ppc64, ppc64el, riscv64, s390x, sparc64], 1:20230520-dev-1 [alpha, sh4, x32])
- GNU Circuit Analysis package, main executable
- gnucap-common (1:20230520-dev-1)
- GNU Circuit Analysis package, development headers
- gnucap-default-plugins0 (1:20230520-dev-1+b1 [amd64, arm64, armel, armhf, hppa, i386, ia64, m68k, mips64el, ppc64, ppc64el, riscv64, s390x, sparc64], 1:20230520-dev-1 [alpha, sh4, x32])
- GNU Circuit Analysis package, default plugins
- qflow (1.4.62+dfsg.1-1~exp1)
- Open-Source Digital Synthesis Flow
- qflow-tech-osu018 (1.4.62+dfsg.1-1~exp1)
- Technology files needed for qflow for osu018
- qflow-tech-osu035 (1.4.62+dfsg.1-1~exp1)
- Technology files needed for qflow for osu035
- qflow-tech-osu050 (1.4.62+dfsg.1-1~exp1)
- Technology files needed for qflow for osu050
- yosys (0.33-6~exp2+b1 [armel, armhf, m68k], 0.33-6~exp2 [alpha, amd64, arm64, i386, mips64el, ppc64el, riscv64, sh4, x32])
- Framework for Verilog RTL synthesis
- yosys-abc (0.33-6~exp2+b1 [armel, armhf, m68k], 0.33-6~exp2 [alpha, amd64, arm64, i386, mips64el, ppc64el, riscv64, sh4, x32])
- Sequential Logic Synthesis and Verification Algorithms
- yosys-dev (0.33-6~exp2+b1 [armel, armhf, m68k], 0.33-6~exp2 [alpha, amd64, arm64, i386, mips64el, ppc64el, riscv64, sh4, x32])
- Framework for Verilog RTL synthesis (development files)