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Pakket: opensta-dev (0~20191111gitc018cb2+dfsg-1)

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Gate-level Static Timing Analyzer - development files

After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs.

It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.

This package contains the header files and some libraries for development.

Tags: Softwareontwikkeling: Bibliotheken, Role: Development Library

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Pakket downloaden voor alle beschikbare platforms
Platform Pakketgrootte Geïnstalleerde grootte Bestanden
amd64 1.184,9 kB9.937,0 kB [overzicht]
arm64 1.139,6 kB9.848,0 kB [overzicht]
armel 1.119,4 kB8.448,0 kB [overzicht]
armhf 1.130,8 kB7.795,0 kB [overzicht]
i386 1.282,1 kB8.585,0 kB [overzicht]
mips64el 1.327,7 kB12.383,0 kB [overzicht]
mipsel 1.287,3 kB9.343,0 kB [overzicht]
ppc64el 1.266,7 kB11.260,0 kB [overzicht]
s390x 1.078,3 kB9.765,0 kB [overzicht]