Package: iverilog (13.0-1 and others)

[ Source: iverilog  ]

Icarus verilog compiler

Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

Tags: Field: Electronics, Implemented in: C++, User Interface: interface::commandline, role::program

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Download iverilog

Download for all available architectures

Architecture	Version	Package Size	Installed Size	Files
alpha (unofficial port)	13.0-1	2,051.4 kB	9,688.0 kB	[list of files]
amd64	13.0-1	2,275.1 kB	8,557.0 kB	[list of files]
arm64	13.0-1	2,006.1 kB	9,088.0 kB	[list of files]
armhf	13.0-1	2,015.9 kB	6,887.0 kB	[list of files]
hppa (unofficial port)	13.0-1	2,060.2 kB	7,992.0 kB	[list of files]
i386	13.0-1	2,357.2 kB	8,562.0 kB	[list of files]
ia64 (unofficial port)	12.0-2+b1	2,129.2 kB	11,793.0 kB	[list of files]
loong64	13.0-1	2,145.2 kB	9,270.0 kB	[list of files]
m68k (unofficial port)	13.0-1	1,896.9 kB	7,718.0 kB	[list of files]
ppc64 (unofficial port)	13.0-1	2,200.3 kB	11,007.0 kB	[list of files]
ppc64el	13.0-1	2,237.5 kB	10,430.0 kB	[list of files]
riscv64	13.0-1	2,209.6 kB	7,317.0 kB	[list of files]
s390x	13.0-1	2,190.6 kB	8,635.0 kB	[list of files]
sh4 (unofficial port)	13.0-1	2,108.7 kB	7,855.0 kB	[list of files]
sparc64 (unofficial port)	13.0-1	1,908.6 kB	25,353.0 kB	[list of files]
x32 (unofficial port)	13.0-1	2,280.2 kB	7,994.0 kB	[list of files]