Package: covered (0.7.10-7)

[ Source: covered  ]

Verilog code coverage analysis tool

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

Tags: Field: Electronics, Implemented in: C, User Interface: interface::commandline, interface::graphical, X Window System, Role: Program, Interface Toolkit: uitoolkit::tk, use::viewing, X Window System: Application

Other Packages Related to covered

• dep: libc6 (>= 2.34)

  GNU C 라이브러리: 공유 라이브러리
  also a virtual package provided by libc6-udeb

• dep: libtcl8.6 (>= 8.6.0)

  Tcl (Tool Command Language) v8.6 - 런타임 라이브러리 파일들

• dep: libtk8.6 (>= 8.6.0)

  Tk toolkit for Tcl and X11 v8.6 - run-time files

• dep: tklib

  standard Tk Library

• dep: zlib1g (>= 1:1.1.4)

  압축 라이브러리 - 런타임

• rec: iverilog

  Icarus verilog compiler

  or verilog

  virtual package provided by iverilog

  or gplcver (>= 2.12a-1.1)

  Verilog simulator

Download covered

Download for all available architectures

Architecture	Package Size	Installed Size	Files
amd64	540.8 kB	2,462.0 kB	[list of files]
arm64	461.1 kB	2,494.0 kB	[list of files]
armhf	463.5 kB	1,955.0 kB	[list of files]
i386	543.0 kB	2,603.0 kB	[list of files]
ppc64el	515.8 kB	2,942.0 kB	[list of files]
riscv64	513.4 kB	2,170.0 kB	[list of files]
s390x	518.3 kB	2,554.0 kB	[list of files]