Package: yosys-abc (0.52-2 and others)

[ Source: yosys  ]

Sequential Logic Synthesis and Verification Algorithms

ABC is a system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.

This is a fork of berkeley-abc maintained by the YosysHQ team for use in the yosys RTL synthesis framework.

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Download yosys-abc

Download for all available architectures

Architecture	Version	Package Size	Installed Size	Files
alpha (unofficial port)	0.52-2	4,581.5 kB	14,403.0 kB	[list of files]
amd64	0.52-2	4,828.6 kB	12,925.0 kB	[list of files]
arm64	0.52-2	4,271.9 kB	12,054.0 kB	[list of files]
armel	0.52-2	4,084.7 kB	11,854.0 kB	[list of files]
armhf	0.52-2	4,254.2 kB	8,910.0 kB	[list of files]
i386	0.52-2	4,902.4 kB	13,881.0 kB	[list of files]
loong64 (unofficial port)	0.52-2	4,554.8 kB	13,077.0 kB	[list of files]
m68k (unofficial port)	0.52-2	4,525.7 kB	13,240.0 kB	[list of files]
mips64el	0.52-2	4,414.2 kB	15,073.0 kB	[list of files]
ppc64el	0.52-2	4,906.7 kB	15,382.0 kB	[list of files]
riscv64	0.52-2	4,798.1 kB	10,774.0 kB	[list of files]
sh4 (unofficial port)	0.33-6	5,831.5 kB	13,788.0 kB	[list of files]
x32 (unofficial port)	0.52-2	4,814.7 kB	12,689.0 kB	[list of files]