Package: yosys-abc (0.52-2) [debports]

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Sequential Logic Synthesis and Verification Algorithms

ABC is a system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.

This is a fork of berkeley-abc maintained by the YosysHQ team for use in the yosys RTL synthesis framework.

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Download yosys-abc

Download for all available architectures

Architecture	Package Size	Installed Size	Files
alpha (unofficial port)	4,581.5 kB	14,403.0 kB	[list of files]