Package: verilator (4.010-1)

[ Source: verilator  ]

fast free Verilog simulator

Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.

Tags: Field: Elektronika, Implemented in: C++, implemented-in::perl, interface::commandline, Role: Program, Purpose: Simulating

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Download verilator

Download for all available architectures

Architecture	Package Size	Installed Size	Files
amd64	3,465.5 kB	16,893.0 kB	[list of files]
arm64	3,116.5 kB	16,505.0 kB	[list of files]
armhf	2,891.3 kB	10,574.0 kB	[list of files]
i386	3,634.7 kB	15,056.0 kB	[list of files]