Package: opensta-dev (0~20191111gitc018cb2+dfsg-1)
Links for opensta-dev
Download Source Package opensta:
- Homepage [github.com]
Gate-level Static Timing Analyzer - development files
After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs.
It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.
This package contains the header files and some libraries for development.
|Architecture||Package Size||Installed Size||Files|
|amd64||1,184.9 kB||9,937.0 kB||[list of files]|
|arm64||1,139.6 kB||9,848.0 kB||[list of files]|
|armel||1,119.4 kB||8,448.0 kB||[list of files]|
|armhf||1,130.8 kB||7,795.0 kB||[list of files]|
|i386||1,282.1 kB||8,585.0 kB||[list of files]|
|mips64el||1,327.7 kB||12,383.0 kB||[list of files]|
|mipsel||1,287.3 kB||9,343.0 kB||[list of files]|
|ppc64el||1,266.7 kB||11,260.0 kB||[list of files]|
|s390x||1,078.3 kB||9,765.0 kB||[list of files]|