Paketti: myhdl-cosimulation (0.10-2)

[ Source: myhdl  ]

MyHDL cosimulation files

MyHDL turns Python into a hardware description and verification language, providing hardware engineers with the power of the Python ecosystem.

Python can then be used as an event-driven simulator using Python decorators actively to specify what corresponds to 'processes' in Verilog / VHDL and thereby achieve concurrency.

This package provides the sources for executable extensions of the core modules.

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Arkkitehtuuri	Paketin koko	Koko asennettuna	Tiedostot
all	14.3 kt	150.0 kt	[tiedostoluettelo]