Package: covered (0.7.10-4) [debports]

[ Source:  ]

Verilog code coverage analysis tool

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

Other Packages Related to covered

• dep: libc6 (>= 2.34)

  GNU C Library: Shared libraries
  also a virtual package provided by libc6-udeb

• dep: libtcl8.6 (>= 8.6.0)

  Tcl (the Tool Command Language) v8.6 - run-time library files

• dep: libtk8.6 (>= 8.6.0)

  Tk toolkit for Tcl and X11 v8.6 - run-time files

• dep: tklib

  standard Tk Library

• dep: zlib1g (>= 1:1.1.4)

  compression library - runtime

• rec: iverilog

  Icarus verilog compiler

  or verilog

  virtual package provided by iverilog

  or gplcver (>= 2.12a-1.1)

  Verilog simulator

Download covered

Download for all available architectures

Architecture	Package Size	Installed Size	Files
hppa (unofficial port)	503.0 kB	2,358.0 kB	[list of files]