Software Packages in "experimental", Subsection electronics
- gnucap (1:20230520-dev-1)
- GNU Circuit Analysis package, main executable
- gnucap-common (1:20230520-dev-1)
- GNU Circuit Analysis package, development headers
- gnucap-default-plugins0 (1:20230520-dev-1)
- GNU Circuit Analysis package, default plugins
- graywolf (0.1.6-4.1~exp1)
- Placement for digital VLSI design
- librnd4-cloud (4.1.1-1.1~exp1)
- Networking plugins for accessing remote resources.
- librnd4-dev (4.1.1-1.1~exp1)
- Ringdove 2D cad library, files for development.
- librnd4-doc (4.1.1-1.1~exp1)
- Documentation for librnd.
- librnd4-hid-gtk4-gl (4.1.1-1.1~exp1)
- GUI: gtk4, opengl
- librnd4-hid-lesstif (4.1.1-1.1~exp1)
- GUI: motif/lesstif, software render
- librnd4-lib-gl (4.1.1-1.1~exp1)
- Support library for rendering with opengl.
- librnd4-lib-gui (4.1.1-1.1~exp1)
- Support library for building the GUI.
- librnd4-pixmap (4.1.1-1.1~exp1)
- Import and export pixmap images.
- librnd4t64 (4.1.1-1.1~exp1)
- Ringdove 2D CAD library framework
- ow-shell (3.2p4+dfsg1-4.3~exp1)
- shell utilities to talk to an 1-Wire owserver
- ow-tools (3.2p4+dfsg1-4.3~exp1)
- tools to monitor or inspect a ow-server link
- owfs (3.2p4+dfsg1-4.3~exp1)
- Dallas 1-wire support
- owfs-common (3.2p4+dfsg1-4.3~exp1)
- common files used by any of the OWFS programs
- owfs-fuse (3.2p4+dfsg1-4.3~exp1)
- 1-Wire filesystem
- owftpd (3.2p4+dfsg1-4.3~exp1)
- FTP daemon providing access to 1-Wire networks
- owhttpd (3.2p4+dfsg1-4.3~exp1)
- HTTP daemon providing access to 1-Wire networks
- owserver (3.2p4+dfsg1-4.3~exp1)
- Backend server for 1-Wire control
- qflow (1.4.62+dfsg.1-1~exp1)
- Open-Source Digital Synthesis Flow
- qflow-tech-osu018 (1.4.62+dfsg.1-1~exp1)
- Technology files needed for qflow for osu018
- qflow-tech-osu035 (1.4.62+dfsg.1-1~exp1)
- Technology files needed for qflow for osu035
- qflow-tech-osu050 (1.4.62+dfsg.1-1~exp1)
- Technology files needed for qflow for osu050
- yosys (0.33-6~exp2)
- Framework for Verilog RTL synthesis
- yosys-abc (0.33-6~exp2)
- Sequential Logic Synthesis and Verification Algorithms
- yosys-dev (0.33-6~exp2)
- Framework for Verilog RTL synthesis (development files)