Package: iverilog (10.2-1.1)

[ Source: iverilog  ]

Icarus verilog compiler

Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

Tags: Field: Electronics, Implemented in: C++, User Interface: interface::commandline, role::program

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Architecture	Package Size	Installed Size	Files
amd64	1,798.2 kB	6,267.0 kB	[list of files]
arm64	1,611.1 kB	6,024.0 kB	[list of files]
armhf	1,557.7 kB	4,153.0 kB	[list of files]
i386	1,883.2 kB	6,335.0 kB	[list of files]