Пакет: verilator (4.010-1)

[ Източник: verilator  ]

fast free Verilog simulator

Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.

Етикети: Field: Електроника, Implemented in: C++, implemented-in::perl, interface::commandline, Role: Program, Purpose: Simulating

Други пакети, свързани с verilator

• dep: libc6 (>= 2.28)

  GNU C Library: Shared libraries
  също и виртуален пакет, предлаган от libc6-udeb

• dep: libgcc1 (>= 1:3.5)

  GCC support library

• dep: libstdc++6 (>= 5.2)

  GNU Standard C++ Library v3

• rec: libsystemc-dev

  Development files for SystemC library

• sug: gtkwave

  VCD (Value Change Dump) file waveform viewer

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Архитектура	Големина на пакета	Големина след инсталиране	Файлове
armhf	2 891,3 кБ	10 574,0 кБ	[списък на файловете]