Package: covered (0.7.10-1)

[ Source: covered  ]

Verilog code coverage analysis tool

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

Tags: Field: Electronics, Implemented in: C, User Interface: interface::commandline, interface::x11, Role: Program, Interface Toolkit: Tk, Purpose: use::viewing, x11::application

Other Packages Related to covered

• dep: libc6.1 (>= 2.7)

  Embedded GNU C Library: Shared libraries
  also a virtual package provided by libc6.1-udeb

• dep: tcl8.5 (>= 8.5.0)

  Tcl (the Tool Command Language) v8.5 - run-time files

• dep: tk8.5 (>= 8.5.0)

  Tk toolkit for Tcl and X11, v8.5 - run-time files

• dep: tklib

  standard Tk Library

• dep: zlib1g (>= 1:1.1.4)

  压缩库 - 运行时

• rec: iverilog

  Icarus verilog compiler

  or verilog

  Icarus verilog compiler (transitional package)

  or gplcver (>= 2.12a-1.1)

  Verilog simulator

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Architecture	Package Size	Installed Size	Files
ia64	1,164.3 kB	4,140.0 kB	[list of files]