Package: iverilog (0.9.2-2)

[ Source: iverilog  ]

Icarus verilog compiler

Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

Tags: Field: Electronics, Implemented in: C++, User Interface: Command Line, Role: Program

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Download iverilog

Download for all available architectures

Architecture	Package Size	Installed Size	Files
sparc	1,334.9 kB	3,728.0 kB	[list of files]