Hämta källkodspaketet iverilog:
Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.
The compiler can target either simulation, or netlist (EDIF).
This is a dummy transitional package that will ensure a proper upgrade path. This package may be safely removed after upgrading.
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| Arkitektur | Version | Paketstorlek | Installerad storlek | Filer |
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| all | 0.9.1-2 | 5,6 kbyte | 32 kbyte | [filförteckning] |
| avr32 (inofficiell anpassning) | 0.8.6-1 | 911,2 kbyte | 2428 kbyte | [filförteckning] |
| m68k (inofficiell anpassning) | 0.8.6-1 | 782,9 kbyte | 2252 kbyte | [filförteckning] |