Stiahnuť zdrojový balík iverilog:
Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.
The compiler can target either simulation, or netlist (EDIF).
This is a dummy transitional package that will ensure a proper upgrade path. This package may be safely removed after upgrading.
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| Architektúra | Verzia | Veľkosť balíka | Nainštalovaná veľkosť | Súbory |
|---|---|---|---|---|
| all | 0.9.1-2 | 5.6 kB | 32 kB | [zoznam súborov] |
| avr32 (neoficiálny port) | 0.8.6-1 | 911.2 kB | 2428 kB | [zoznam súborov] |
| m68k (neoficiálny port) | 0.8.6-1 | 782.9 kB | 2252 kB | [zoznam súborov] |