Zawęź do gałęzi: [buster] [buster-updates] [buster-backports] [bullseye] [bullseye-updates] [bullseye-backports] [bookworm] [bookworm-updates] [bookworm-backports] [trixie] [sid] [experimental]
Zawęź do architektury [alpha] [amd64] [arm] [arm64] [armel] [armhf] [avr32] [hppa] [hurd-i386] [i386] [ia64] [kfreebsd-amd64] [kfreebsd-i386] [m68k] [mips] [mips64el] [mipsel] [powerpc] [powerpcspe] [ppc64] [ppc64el] [riscv64] [s390] [s390x] [sh4] [sparc] [sparc64] [x32]
Szukano pakietów których nazwy zawierają yosys w wszystkich gałęziach, wszystkich sekcjach i wszystkich architekturach. Liczba pasujących pakietów: 7.
Dokładne dopasowania
Pakiet yosys
- buster (oldoldstable) (electronics):
Framework for Verilog RTL synthesis
0.8-1: amd64 arm64 armhf i386 - bullseye (oldstable) (electronics):
Framework for Verilog RTL synthesis
0.9-1+b1: amd64 arm64 armel armhf i386 mips64el mipsel ppc64el s390x - bookworm (stable) (electronics):
Framework for Verilog RTL synthesis
0.23-6: amd64 arm64 armel armhf i386 mips64el mipsel ppc64el - sid (unstable) (electronics):
Framework for Verilog RTL synthesis
0.33-5+b3: riscv64
0.33-5+b2: alpha amd64 arm64 armel armhf i386 m68k mips64el ppc64el sh4 x32
0.23-6 [debports]: ia64
0.12-1 [debports]: hppa
0.9-2+b1 [debports]: ppc64
0.6-7+b1 [debports]: sparc64 - experimental (electronics):
Framework for Verilog RTL synthesis
0.33-6~exp2+b1: armel armhf m68k riscv64 sh4
0.33-6~exp2 [debports]: alpha amd64 arm64 i386 mips64el ppc64el x32
Inne wyniki
Pakiet yosys-abc
- sid (unstable) (electronics):
Sequential Logic Synthesis and Verification Algorithms
0.33-5+b3: riscv64
0.33-5+b2 [debports]: alpha amd64 arm64 armel armhf i386 m68k mips64el ppc64el sh4 x32 - experimental (electronics):
Sequential Logic Synthesis and Verification Algorithms
0.33-6~exp2+b1: armel armhf m68k riscv64 sh4
0.33-6~exp2: alpha amd64 arm64 i386 mips64el ppc64el x32
Pakiet yosys-abc-dbgsym
- sid (unstable) (debug):
debug symbols for yosys-abc
0.33-5+b2 [debports]: alpha m68k sh4 x32 - experimental (debug):
debug symbols for yosys-abc
0.33-6~exp2+b1 [debports]: m68k sh4
0.33-6~exp2 [debports]: alpha x32
Pakiet yosys-dbgsym
- sid (unstable) (debug):
debug symbols for yosys
0.33-5+b2 [debports]: alpha m68k sh4 x32
0.23-6 [debports]: ia64 riscv64
0.12-1 [debports]: hppa
0.9-2+b1 [debports]: ppc64
0.6-7+b1 [debports]: sparc64 - experimental (debug):
debug symbols for yosys
0.33-6~exp2+b1 [debports]: m68k sh4
0.33-6~exp2 [debports]: alpha x32
Pakiet yosys-dev
- buster (oldoldstable) (electronics):
Framework for Verilog RTL synthesis (development files)
0.8-1: amd64 arm64 armhf i386 - bullseye (oldstable) (electronics):
Framework for Verilog RTL synthesis (development files)
0.9-1+b1: amd64 arm64 armel armhf i386 mips64el mipsel ppc64el s390x - bookworm (stable) (electronics):
Framework for Verilog RTL synthesis (development files)
0.23-6: amd64 arm64 armel armhf i386 mips64el mipsel ppc64el - sid (unstable) (electronics):
Framework for Verilog RTL synthesis (development files)
0.33-5+b3: riscv64
0.33-5+b2: alpha amd64 arm64 armel armhf i386 m68k mips64el ppc64el sh4 x32
0.23-6 [debports]: ia64
0.12-1 [debports]: hppa
0.9-2+b1 [debports]: ppc64
0.6-7+b1 [debports]: sparc64 - experimental (electronics):
Framework for Verilog RTL synthesis (development files)
0.33-6~exp2+b1: armel armhf m68k riscv64 sh4
0.33-6~exp2: alpha amd64 arm64 i386 mips64el ppc64el x32
Pakiet yosys-doc
- buster (oldoldstable) (doc):
Documentation for Yosys
0.8-1: all - bullseye (oldstable) (doc):
Documentation for Yosys
0.9-1: all - bookworm (stable) (doc):
Documentation for Yosys
0.23-6: all - sid (unstable) (doc):
Framework for Verilog RTL synthesis (documentation)
0.33-5: all - experimental (doc):
Framework for Verilog RTL synthesis (documentation)
0.33-6~exp2: all
Pakiet yosys-plugin-ghdl
- sid (unstable) (electronics):
VHDL to RTL synthesis plugin using GHDL
0.0~git20230419.5b64ccf-1: amd64 i386
0.0~git20211127.09a32cd-3: arm64 armel mips64el ppc64el