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[ Source: vbs  ]

Package: vbs (1.4.0-7)

Verilog Behavioral Simulation

Verilog is a Hardware Description Language used mostly for digital circuit design and simulation. This program is a simple implementation of a Verilog simulator. VBS tries to implement all of the Verilog behavioral constructs that are synthesizable, but still allow complex test vectors for simulation.

Other Packages Related to vbs

  • depends
  • recommends
  • suggests
  • dep: libc6 (>= 2.3.2.ds1-4) [not alpha, ia64]
    GNU C Library: Shared libraries and Timezone data
    also a virtual package provided by libc6-udeb
  • dep: libc6.1 (>= 2.3.2.ds1-4) [alpha, ia64]
    GNU C Library: Shared libraries and Timezone data
    also a virtual package provided by libc6.1-udeb
  • dep: libgcc1 (>= 1:3.3.4-1) [hppa, m68k]
    GCC support library
    dep: libgcc1 (>= 1:3.4.1-3) [not hppa, ia64, m68k]
    dep: libgcc1 (>= 1:3.4.3-6) [ia64]
  • dep: libstdc++5 (>= 1:3.3.4-1)
    The GNU Standard C++ Library v3
  • dep: zlib1g (>= 1:1.2.1) [i386]
    compression library - runtime
    also a virtual package provided by zlib1g-udeb

Download vbs

Download for all available architectures
Architecture Package Size Installed Size Files
alpha 543.8 kB1972 kB [list of files]
amd64 (unofficial port) 342.6 kB908 kB [list of files]
arm 332.8 kB1140 kB [list of files]
hppa 402.0 kB1388 kB [list of files]
i386 347.1 kB920 kB [list of files]
ia64 357.7 kB1568 kB [list of files]
m68k 278.3 kB888 kB [list of files]
mips 331.9 kB1396 kB [list of files]
mipsel 329.5 kB1396 kB [list of files]
powerpc 278.2 kB996 kB [list of files]
s390 279.9 kB1060 kB [list of files]
sparc 273.4 kB840 kB [list of files]