パッケージ: verilog (0.9.1-2)

Icarus verilog compiler (transitional package)

Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

This is a dummy transitional package that will ensure a proper upgrade path. This package may be safely removed after upgrading.

タグ: ソフトウェア開発: コンパイラ, 分野: 電子工学, ユーザインタフェース: テキストベースの対話, 役割: プログラム, 対象範囲: ユーティリティ, インタフェースツールキット: Ncurses TUI