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Package: verilog (0.9.1-2 and others)

Icarus verilog compiler (transitional package)

Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

This is a dummy transitional package that will ensure a proper upgrade path. This package may be safely removed after upgrading.

Tags: Software Development: Compiler, Field: Elektronika, User Interface: Text-based Interactive, Role: Program, Scope: Utility, Interface Toolkit: Ncurses TUI

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Download verilog

Download for all available architectures
Architecture Version Package Size Installed Size Files
all 0.9.1-2 5.6 kB32 kB [list of files]
avr32 (unofficial port) 0.8.6-1 911.2 kB2428 kB [list of files]
m68k (unofficial port) 0.8.6-1 782.9 kB2252 kB [list of files]