Télécharger le paquet source iverilog :
Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.
The compiler can target either simulation, or netlist (EDIF).
This is a dummy transitional package that will ensure a proper upgrade path. This package may be safely removed after upgrading.
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| Architecture | Taille du paquet | Espace occupé une fois installé | Fichiers |
|---|---|---|---|
| all | 5,6 ko | 32 ko | [liste des fichiers] |