etch  ] [  etch-m68k  ] [  lenny  ] [  squeeze  ] [  sid  ]
[ Source: iverilog  ]

Paketti: verilog (0.9.1-2)

Icarus verilog compiler (transitional package)

Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

This is a dummy transitional package that will ensure a proper upgrade path. This package may be safely removed after upgrading.

Tagit: Software Development: Compiler, Field: Elektroniikka, User Interface: Text-based Interactive, Role: Program, Scope: Utility, Interface Toolkit: Ncurses TUI

Muut pakettiin verilog liittyvät paketit

  • depends
  • recommends
  • suggests

Imuroi verilog

Imurointi kaikille saataville arkkitehtuureille
Arkkitehtuuri Paketin koko Koko asennettuna Tiedostot
all 5.6 kt32 kt [tiedostoluettelo]